As is known in the art, printed wiring boards (PWB) which require multiple plating operations in some areas of the PWB and which have etched circuits with small tolerances consisting of fine lines and/or fine gaps in other areas of the PWB are relatively difficult to fabricate. Similarly, any PWBs having etched circuits or other structures (e.g. hairpin bandpass filter structures) and multiple plating steps are also relatively difficult to fabricate.
To fabricate such PWBs, prior art techniques carefully monitor fabrication/etching processes. Detail prints (i.e. fabrication drawings) define a final top layer plating thickness and also define an etch accuracy for certain top layer board features. Prior art techniques have utilized “plate up then sand down” types of processes to control the final top layer plating thickness everywhere on the PWB surface. While this approach does work, it has yield and reliability issues and is very labor intensive. If too much sanding is done, the PWB can fail an inspection (or tests, e.g. a via plate wrap tests and/or other tests) and be rejected (i.e. deemed not suitable for use in an intended application). On the other hand, if not enough sanding is done, the PWB can fail etch accuracy and maximum plating thickness tests and once again be rejected. As a result, a manufacturer (such as a fabrication or assembly house) may have to procure and produce additional duplicate PWBs in order to deliver one PWB which passes all inspections/tests and meets all of a purchaser's requirements, including critical operational requirements. PWB's which do not pass the required inspections/tests go unused. This results in wasted PWBs and higher unit cost per PWB.